1. Field of the Invention
The present invention generally relates to a fabricating process of a chip package structure. More particularly, the present invention relates to a fabricating process of a chip package structure utilizing at least two B-staged adhesive layers to bond substrates.
2. Description of Related Art
Following the increase of input/output contacts of an integrated circuit, chip package technology has become more and more diversified. This is due to the fact that Flip Chip (FC) Interconnect technology minimizes the thickness of the chip package, and reduces signal transmission path, etc. The most common used chip package structures applying the flip chip interconnect technology is, for example, Flip Chip Ball Grid Array (FC/BGA) package and the Flip Chip Pin Grid Array (FC/PGA) package.
Flip chip interconnect technology employs the method of defining area array by disposing a plurality of bonding pads onto the active surface of the chip and forming a plurality of bumps on the bonding pads, respectively. Next, the chip is flipped to connect the bonding bumps of the chip and a plurality of contact pads disposed on a carrier such as a circuit substrate. Therefore, the chip is electrically and mechanically connected to the carrier through the bumps. Further, the chip can be electrically connected to external electronic devices via the internal circuits of the carrier. Generally speaking, the bumps has several types such as the solder bump, the gold bump, the copper bump, the conductive polymer bump, the polymer bump, etc.
FIG. 1 is a schematic cross-sectional view showing a flip chip package structure having polymer bumps. Referring to FIG. 1, the flip chip package structure 100 comprises a substrate 110, a plurality of polymer bumps 120, a chip 130 and solder 140. The substrate 110 has a surface 110a and a plurality of contact pads 112 disposed on the surface 110a. The chip 130 has an active surface 130a and a plurality of bonding pads 132 disposed on the active surface 130a. The polymer bumps 120 made of polymer material with conductive property are respectively arranged between the contact pads 112 and the bonding pads 132 for electrically connecting the substrate 110 and the chip 130. The surface A of the solder 140 is adhered to the contact pad 112 and the surface B of the solder 140 is adhered to the polymer bump 120. Therefore, when external force or thermal stress (not shown) is applied to the flip chip package structure 100, the solder 140 may peel from the contact pads 112 such that the polymer bumps 120 can not be electrically connected to the contact pads 112. Obviously, the reliability of the flip chip package structure 100 is lower.